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PRELIMINARY TECHNICAL DATA
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SPI/I2C Compatible, 10-Bit Digital Temperature Sensor and Quad Voltage Output 12/10/8-Bit DAC
Preliminary Technical Data
FEATURES ADT7316 - Four 12-Bit DACs ADT7317 - Four 10-Bit DACs ADT7318 - Four 8-Bit DACs Buffered Voltage Output Guaranteed Monotonic By Design Over All Codes 10-Bit Temperature to Digital Converter Temperature range: -40oC to +125oC Temperature Sensor Accuracy of 0.5oC Supply Range : + 2.7 V to + 5.5 V DAC Output Range: 0 - 2VREF Power-Down Current 1A Internal 2.25 VRef Option Double-Buffered Input Logic Buffered / Unbuffered Reference Input Option Power-on Reset to Zero Volts Simultaneous Update of Outputs (LDAC Function) On-Chip Rail-to-Rail Output Buffer Amplifier I2C, SPITM, QSPITM, MICROWIRETM and DSP-Compatible 4wire Serial Interface 16-Lead QSOP Package APPLICATIONS Portable Battery Powered Instruments Personal Computers Telecommunications Systems Electronic Test Equipment Domestic Appliances Process Control
ON-CHIP TEMPERA TURE SENSOR D+ DINTERNAL TEMPERATURE VA LUE REGISTER
ADT7316/7317/7318
GENERAL DESCRIPTION
The ADT7316/7317/7318 combines a 10-Bit Temperature-to-Digital Converter and a quad 12/10/8-Bit DAC respectively, in a 16-Lead QSOP package. This includes a bandgap temperature sensor and a 10-bit ADC to monitor and digitize the temperature reading to a resolution of 0.25oC. The ADT7316/17/18 operates from a single +2.7V to +5.5V supply. The output voltage of the DAC ranges from 0 V to 2VREF , with an output voltage settling time of typ 7 msec. The ADT7316/17/18 provides two serial interface options, a four-wire serial interface which is compatible with SPITM, QSPITM, MICROWIRETM and DSP interface standards; and a two-wire I2C interface. It features a standby mode that is controlled via the serial interface. The reference for the four DACs is derived either internally or from two reference pins (one per DAC pair) .The outputs of all DACs may be updated simultaneously using the software LDAC function or external LDAC pin. The ADT7316/7317/7318 incorporates a power-on-reset circuit, which ensures that the DAC output powers-up to zero volts and it remains there until a valid write takes place. The ADT7316/7317/7318's wide supply voltage range, low supply current and SPI/I2C-compatible interface, make it ideal for a variety of applications, including personal computers, office equipment and domestic appliances.
ADDRESS POINTER REGISTER TH IGH LIMIT REGISTERS T L OW L IMIT REGISTERS V D D L im it REGISTERS CONTROL CONFIG . 1 REGISTER CONTROL CONFIG. 2 REGISTER CONTROL CONFIG . 3 REGISTER DAC D REGISTERS STRING DA C D DAC A REGISTERS STRING DAC A
2
V OUT -A
DIGITA L MUX
7 8
ANAL OG MUX
A -TO-D CONVERTER
VD D VA LUE REGISTER
LIMIT COMPARATOR
DIGITAL MUX
DA C B REG ISTERS
STRING DA C B
1
V OUT -B
VD D SENSOR
EXTERNA L TEMPERATURE VALUE REGISTER
DAC C REGISTERS
STRING DA C C
16 VOUT-C
15 VOUT-D
ADT7316/17/18
STA TUS REGISTERS
DA C CONFIGURATION REGISTER L DA C CONFIGURATION REGISTER INTERRUPT MASK REGISTERS
GAIN SELECT LO GIC
POWER DOWN L OGIC
10 INTERRUPT
SMB us/SPI INTERFACE
INTERNAL TEMP SENSOR
6
VD D
5
GND
4
CS
13
SCL/SCL K
12
11
9
LDAC
3
V R EF -A B
14
V R EF -CD
SDA /DIN DOUT/ADD
FUNCTIONAL BLOCK DIAGRAM
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
I2C is a registered trademark of Philips Corporation * Protected by U.S. Patent No. 5,969,657; other patents pending. SPI and QSPI are trademarks of Motorola, INC. MICROWIRE is a trademark of National Semiconductor Corporation. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA ADT7316/ADT7317/ADT7318-SPECIFICATIONS1
(VDD=2.7 V to 5.5 V, GND=0 V, REFIN=2.25 V, unless otherwise noted) Parameter 2
DAC DC PERFORMANCE ADT7318 Resolution Relative Accuracy Relative Accuracy Differential Nonlinearity ADT7317 Resolution Relative Accuracy Relative Accuracy Differential Nonlinearity ADT7316 Resolution Relative Accuracy Relative Accuracy Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Lower Deadband
3,4
Min
Typ
Max
Units
Conditions/Comments
8 0.15 tbd 0.02 10 0.5 tbd 0.05 12 2 tbd 0.02 0.4 0.3 20 tbd -12 -5 -60 200
1 tbd 0.25
Bits LSB LSB LSB Bits LSB LSB LSB Bits LSB LSB LSB % of FSR LSB % of FSR LSB mV mV
Excluding Offset and Gain errors Guaranteed Monotonic by design over all codes
4 tbd 0.5
Excluding Offset and Gain errors Guaranteed Monotonic by design over all codes
16 tbd 0.9 3 0.5 1.25 0.5 60 tbd
Excluding Offset and Gain errors Guaranteed Monotonic by design over all codes
Upper Deadband Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk6
THERMAL CHARACTERISTICS
Lower Deadband exists only if Offset Error is Negative. See Figure 5. Upper Deadband exists if VREF = VDD and Offset plus Gain Error is positive. See Figure 6.
ppm of FSR/C ppm of FSR/C dB VDD = 10% V RL = 2 K to GND or VDD
Internal Reference used.
INTERNAL TEMPERATURE SENSOR
Accuracy @ V DD=3.3V Accuracy @ V DD=5V Resolution Long Term Drift EXTERNAL TEMPERATURE SENSOR Accuracy @ V DD=3.3V Accuracy @ V DD=5V Resolution Update Rate, tR TBD TBD TBD 2 3 10 2 3 10 0.5 2 3 C C C C Bits C/1000hrs TA TA TA TA = = = = 0C to +85C -40C to +125C 0C to +85C -40C to +125C
2 3
C C C C Bits s s
External Transistor = 2N3906. TA = 0C to +85C. TA = -40C to +125C TA = 0C to +85C TA = -40C to +125C
Round Robin5 enabled Round Robin disabled
Temperature Conversion Time Output Source Current
180 11
s A A
High Level Low Level
VOLTAGE OUTPUT 8-Bit DAC Output Resolution Scale Factor 10-Bit DAC Output Resolution
1 8.79 17.58 0.25
C mV/C mV/C C -2-
0-VREF Output. TA = -40C to +125C 0-2VREF Output. TA = -40C to +125C
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
Parameter 2 Scale Factor
DAC ERTERNAL REFERENCE INPUT 6 VREF Input Range VREF Input Range VREF Input Impedance
Min
Typ 2.2 4.39
Max
Units mV/C mV/C
Conditions/Comments 0-VREF Output. TA = -40C to +125C 0-2VREF Output. TA = -40C to +125C
1 0.25 37 74
VDD VDD 45 90 >10 -90 -75 2.25 80 V DD -0.001 0.5 25 16 2.5 5 1 0.8 0.6
Reference Feedthrough Channel-toChannel Isolation ON-CHIP REFERENCE Reference Voltage 6 Temperature Coefficient 6 OUTPUT CHARACTERISTICS 6 Output Voltage 7 0.001 DC Output Impedance Short Circuit Current Power Up Time DIGITAL INPUTS 6 Input Current VIL, Input Low Voltage VIH, Input High Voltage Pin Capacitance SCL, SDA Glitch Rejection DIGITAL OUTPUT Output High Voltage, VOH Output Low Voltage, VOL Output High Current, IOH 1.89
V V k k M dB dB V ppm/C V mA mA s s A V V V pF ns
Buffered Reference Mode Unbuffered Reference Mode Unbuffered Reference Mode. 0-2 VREF Output Range. Unbuffered Reference Mode. 0- VREF Output Range. Buffered reference mode and Power-Down Mode Frequency=10KHz Frequency=10KHz
This is a measure of the minimum and maximum drive capability of the output amplifier VDD = +5V VDD = +3V Coming out of Power Down Mode. VDD = +5 V Coming out of Power Down Mode. VDD = +3 V VIN = 0V to VDD VDD = +5V10% VDD = +3V10% All Digital Inputs Input Filtering Suppresses Noise Spikes of Less than 50 ns ISOURCE = ISINK = 200 A IOL = 3 mA VOH = 5 V
3
10 50
2.4 0.4 1
V V mA
Output Capacitance, COUT
ALERT Output Saturation Voltage
50 0.8 2.5 0 50 50 90 0 50 50 35 20 0 0 40 2.7 5.5 50
pF V s ns ns ns ns ns ns ns ns ns ns ns ns V ms
IOUT = 4 mA Fast-Mode I2C. See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2
I2C TIMING CHARACTERISTICS8,9 Serial Clock Period, t1 Data In Setup Time to SCL High, t2 Data Out Stable after SCL Low, t3 SDA Low Setup Time to SCL Low (Start Condition), t4 SDA High Hold Time after SCL High (Stop Condition), t5 SDA and SCL Fall Time, t6 SPI TIMING CHARACTERISTICS10, 11 CS to SCLK Setup Time, t1 SCLK High Pulsewidth, t2 SCLK Low Pulse, t3 Data Access Time after SCLK Falling edge, t412 Data Setup Time Prior to SCLK Rising Edge, t5 Data Hold Time after SCLK Rising Edge, t6 CS to SCLK Hold Time, t7 CS to DOUT High Impedance, t8
POWER REQUIREMENTS VDD VDD Settling Time
VDD settles to within 10% of it's final voltage level.
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
IDD (Normal Mode)13 IDD (Power Down Mode) Power Dissipation 0.85 1 0.5 tbd tbd tbd tbd 1.3 3 1 tbd tbd mA A A W W VIH = VDD and VIL = GND VDD = +4.5V to +5.5V, VIH=VDD and VIL=GND VDD = +2.7V to +3.6V, VIH=VDD and VIL=GND VDD = +2.7 V. Using Normal Mode VDD = +2.7 V. Using Shutdown Mode
Notes: 1 Temperature ranges are as follows: A Version: -40C to +125C. 2 See Terminology. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255) 5 See Terminology. 6 Guaranteed by Design and Characterization, not production tested 7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, VREF=VDD , "Offset plus Gain" Error must be positive. 8 The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I2C specification. Switching off the input filters improves the transfer rate but has a negative affect on the EMC behaviour of the part. 9 Guaranteed by design. Not tested in production. 10 Guaranteed by design and characterization, not production tested. 11 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 12 Measured with the load circuit of Figure 3. 13 IDD spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded. Specifications subject to change without notice.
DAC AC CHARACTERISTICS1
Parameter 2
Output Voltage Settling Time ADT7318 ADT7317 ADT7316 Slew Rate Major-Code Change Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion 6 7 8 0.7 12 0.5 1 0.5 3 200 -70
(VDD = +2.7V to +5.5 V; RL=4k7 to GND; CL=200pF to GND; 4K7 to VDD; All specifications TMIN to TMAX unless otherwise noted.)
Max
8 9 10
Min Typ @ 25C
Units
s s s V/s nV-s nV-s nV-s nV-s nV-s kHz dB
Conditions/Comments
VREF=V DD=+5V 1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex) 1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex) 1/4 Scale to 3/4 Scale change (400 Hex to C00 Hex) 1 LSB change around major carry.
V REF =2V0.1Vpp V REF =2.5V0.1Vpp. Frequency=10kHz.
NOTES 1 Guaranteed by Design and Characterization, not production tested 2 See Terminology Specifications subject to change without notice.
t1 SCL t4 SDA DA T A IN t3 SDA DA T A O U T t6 t2 t5
Figure 1. Diagram for I2C Bus Timing
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
+5
t1
1 SCLK
t2
2
t7
3 4 8
t3
DOU T D BX DBX DBX
t4
DBX DB7 MSB
t8
t6 t5
DIN
DB7 MSB
DB6
DB5
DB0 L SB
DB8 MSB
Figure 2. Diagram for SPI Bus Timing
200 A
IO L
TO O UTPUT P IN
1.6V CL 50pF
200 A
IO L
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
VDD
47 To DAC Ou tp ut 47 200pF
Figure 4. Load Circuit for DAC Outputs
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
ABSOLUTE MAXIMUM RATINGS*
VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead QSOP Package Power Dissipation JA Thermal Impedance Reflow Soldering Peak Temperature Time of Peak Temperature
-0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3V -40C to +125C -65C to +150C +150C (Tj max - TA) / JA 150 C/W (QSOP) +220 +/- 0C 10 sec to 40 sec
Table 1. I2C Address Selection
ADD Pin Low Float High
I2C Address 1001 000 1001 010 1001 011
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION QSOP
Vou t -B Vou t -A V r ef -AB CS GND VDD D+ D1 2 3 4 5 6 7 8 16 Vou t -C 15 Vou t -D 14 Vr ef -CD
ADT7316/ 7317/7318
TO P VIE W
(Not to Scal e)
13 SCL/SCLK 12 SDA/DIN 11 DOUT/ADD 10 INTERRUPT 9 LDAC
ORDERING GUIDE
Model ADT7318ARQ ADT7317ARQ ADT7316ARQ
Temperature Range -40C to +125C -40C to +125C -40C to +125C
DAC Resolution 8-Bits 10-Bits 12-Bits
Package Description 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP
Package Options RQ-16 RQ-16 RQ-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADT7316/7317/7318 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
ADT7316/7317/7318 PIN FUNCTION DESCRIPTION
Pin 1 2 3
Mnemonic VOUTB VOUTA VREFAB
Description Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Reference Input Pin for DACs A and B.It may be configured as a buffered or unbuffered input to each or both of the DACs A and B. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. SPI Active low control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables the input register and data is transferred in and out on the rising edges of the following serial clocks. This pin must be kept high for I2C mode of operation. CS is also used as a control pin when selecting the serial interface type after power-up. Ground Reference Point for All Circuitry on the part. Analog and Digital Ground. Positive Supply Voltage, +2.7 V to +5.5 V.The supply should be decoupled to ground. Positive connection to external temperature sensor Negative connection to external temperature sensor Active low control input that transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Bit C3 of Control Configuration 3 register enables LDAC pin. Default is with LDAC pin controlling the loading of DAC registers. Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when temperature, VDD and AIN limits are exceeded. Default is active low. SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is clocked out at the falling edge of SCLK. ADD, I2C serial bus address selection pin. Logic input. During the first valid I2C bus communication this pin is checked to determine the serial bus address assigned to the ADT7316/17/ 18. Any subsequent changes on this pin will have no affect on the I2C serial bus address. A low on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. SDA - I2C Serial Data Input. I2C serial data to be loaded into the parts registers is provided on this input. DIN - SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on this input. Data is clocked into a register on the rising edge of SCLK. Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of the ADT7316/7317/7318 and also to clock data into any register that can be written to. Reference Input Pin for DACs C and D.It may be configured as a buffered or unbuffered input to each or both of the DACs C and D. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
4
CS
5 6 7 8 9
GND VDD D+ DLDAC
10 11
INTERRUPT DOUT/ADD
12
SDA/DIN
13
SCL/SCLK
14
VREFCD
15 16
VOUTD VOUTC
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
TERMINOLOGY RELATIVE ACCURACY REFERENCE FEEDTHROUGH
Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus Code plots can be seen in TPCs 1, 2, and 3.
DIFFERENTIAL NONLINEARITY
This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs.
CHANNEL-TO-CHANNEL ISOLATION
Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC and Temperature Sensor ADC is guaranteed monotonic by design. Typical DAC DNL versus Code plots can be seen in TPCs 4, 5, and 6.
OFFSET ERROR
This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
This is a measure of the offset error of the DAC and the output amplifier. (See Figures 5 and 6.) It can be negative or positive. It is expressed in mV.
OFFSET ERROR MATCH
Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
DIGITAL FEEDTHROUGH
This is the difference in Offset Error between any two channels.
GAIN ERROR
Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to the. It is specified in nV secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALK
This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.
GAIN ERROR MATCH
This is the difference in Gain Error between any two channels.
OFFSET ERROR DRIFT
This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in stand-alone mode and is expressed in nV secs.
ANALOG CROSSTALK
This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of fullscale range)/C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of fullscale range)/C.
DC POWER-SUPPLY REJECTION RATIO (PSRR)
This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a fullscale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV secs.
DAC-TO-DAC CROSSTALK
This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dBs. VREF is held at 2 V and VDD is varied 10%.
DC CROSSTALK
This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV secs.
MULTIPLYING BANDWIDTH
This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in V.
The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs.
ROUND ROBIN
This term is used to describe the ADT7316/17/18 cycling through the available measurement channels in sequence taking a measurement on each channel.
GAIN ERROR + OFFSET ERROR
OUTPUT VOLTAGE
NEGATIVE OFFSET ERROR
DAC CODE ACTUA L IDEAL
L OWER DEADBAND CODES AMPL IFIER FOOTROOM
NEGATIVE OFFSET ERROR
Figure 5. Transfer Function with Negative Offset
GAIN ERROR + OFFSET ERROR UPPER DEADBAND CODES
OUTPUT VOL TAGE
ACTUAL IDEAL POSITIVE OFFSET ERROR DAC C ODE
FULL SCALE
Figure 6. Transfer Function with Positive Offset (VREF = VDD)
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
1.0 T A = 25 C V DD = 5V 0.5 1 3 TA = 25 C VDD = 5V 2 8 12 T A = 25 C VDD = 5V
INL ERROR - LSB s
4
INL ERROR - L
0
INL ERROR - L
0
0
-1
-4
-0.5 -2 -8
-1.0
0
50
100
150 CODE
200
250
-3
-12 0 200 400 600 CODE 800 1000
0
1000
2000 COD E
3000
4000
TPC 1. ADT7318 Typical INL Plot
TPC 2. ADT7317 Typical INL Plot
TPC 3. ADT7316 Typical INL Plot
0. 3
TA = 2 5 C V DD = 5 V
0.6 TA = 25 C VDD = 5V 0.4
1 TA = 25 C VDD = 5V 0.5
0. 2
D NL ERRO R - L SBs
0. 1
DNL ERROR - LSB s
0.2
DNL ERROR - LSBs
800 1000
0
0
0
-0 1 .
-0.2
-0.5 -0 2 . -0.4
-0 3 . 0
50
10 0 15 0 C ODE
20 0
25
-0.6 0 200 400 600 CODE
-1 0 1000 2000 CODE 3000 4000
TPC 4. ADT7318 Typical DNL Plot
TPC 5. ADT7317 Typical DNL Plot
TPC 6. ADT7316 Typical DNL Plot
0.5
V DD = 5V TA = 25 C M A X INL
0.5 0.4 0.3 0.2
V DD = 5V V REF = 3V MA X INL
1
V DD = 5V V REF = 2V
0.25
0.5
MA X DNL
ERROR - LSBs
0.1 0 -0.1
ERROR - % FSR
ERROR - L SBs
MA X DNL
GA IN E RRO R
0
M IN DNL
0
O F FS ET ERRO R
M IN DNL
-0.2 -0.25
M IN INL
-0.5 -0.3
MIN INL
-0.4 -0.5 0 1 2 3 V REF - V 4 5 -0.5 40 0 40 TEMPERATURE - C 80 120 -1 40 0 40 TEMPERATURE - C 80 120
TPC 7. ADT7318 INL and DNL Error vs VREF
TPC 8. ADT7318 INL Error and DNL Error vs Temperature
TPC 9. ADT7318 Offset Error and Gain Error vs Temperature
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
0.2 0.1 0
TA = 25 C V REF = 2V GA IN ERRO R 5V SO URCE
5
600
4
3V SO URCE
500 T A = 25 C VDD = 5V VREF = 2V
ERROR - % FSR
VOUT - Vo lts
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6
OF FS ET ERRO R
400
3
A
2
IDD 3V SINK 5V SINK
300
200 1
100
0
1
2
3 4 VDD - Vol ts
5
6
0
0
2 5 1 3 4 SINK/SOURCE CURRENT - mA
6
0 ZERO-SCAL E CODE
FULL -SCAL E
TPC 10. Offset Error and Gain Error vs VDD
TPC 11. VOUT Source and Sink Current Capability
TPC 12. Supply Current vs. DAC Code
600 -40 C +25 C 500
0.5
T A = 25 C 5 s V D D = 5V V R EF = 5V V OUT A
0.4
CH1
400
+105 C
A
IDD -
IDD -
300
A
0.3
- 40 C S CLK
0.2
+25 C
200 0.1
CH2
100
+105 C
CH1 1V, CH2 5V, TIME BASE= 1 s/DIV 5.0 5.5
0 2.5
3.0
3.5
4.0 4.5 V DD - Vo lt s
5.0
5.5
0 2.5
3. 0
3.5
4.5 4.0 V DD - Vo lts
TPC 13. Supply Current vs. Supply Volt- TPC 14. Power-Down Current vs. Supply age Voltage
TPC 15. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
2.50 T A = 25 C V DD = 5V V REF = 2V 2.49 V OUT A
10 0 -10
CH1
VOUT - Vol ts
-20
dB
-30 2.4 8 -40 -50 2.47 1 s/DIV -60 0.01
CH2
2,
CH 1 500mV, CH2 5.00V, TIME BASE = 1 s/DIV 0.1 1 10 100 FR EQUENCY - kHz 1k 10k
TPC 16. Exiting Power-Down to Midscale TPC 17. ADT7316 Major-Code Transition TPC 18. Multiplying Bandwidth (SmallGlitch Energy Signal Frequency Response)
REV. PrN
-11-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
0.02
V D D = 5V TA = 25 C
FULL -SCALE ERROR - Vol ts
0.01
0
-0.01
-0.02
0
1
2
3 4 VREF - Vol ts
5
6
1mV/DIV
150n s/DIV
TPC 19. Full-Scale Error vs. VREF
TPC 20. DAC-to-DAC Crosstalk
2
0
1.5
1 TEMPERATURE ERROR ('C 5.5V 0.5
TITLE
0
0 -30 -20 -10 -0.5 0 10 20 30 40 50 60 70 80 90 100 110 120
-1
3.3V
-1.5
0
0
0
0
0 TITLE
0
0
0
-2 TE E A R ('C MP R TU E )
TPC 21. PSRR vs Supply Ripple Frequency
TPC 22. Temperature Error @ 3.3 V and 5.5 V
-12-
REV. PrN
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
FUNCTIONAL DESCRIPTION - DAC The ADT7316/7317/7318 has quad resistor-string DACs fabricated on a CMOS process with a resolutions of 12, 10 and 8 bits respectively. They contain four output buffer amplifiers and is written to via I2C serial interface or SPI serial interface. See Serial Interface Selection section for more information. The ADT7316/7317/7318 operates from a single supply of 2.7 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7V/s. DACs A and B share a common reference input, namely VREFAB. DACs C and D share a common reference input, namely VREFCD. Each reference input may be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from GND to VDD. The devices have a power-down mode, in which all DACs may be turned off completely with a high-impedance output. Each DAC output will not be updated until it receives the LDAC command. Therefore while the DAC registers would have been written to with a new value, this value will not be represented by a voltage output until the DACs have received the LDAC command. Reading back from any DAC register prior to issuing an LDAC command will result in the digital value that corresponds to the DAC output voltage. Thus the digital value written to the DAC register cannot be read back until after the LDAC command has been initiated. This LDAC command can be given by either pulling the LDAC pin low, setting up Bits D4 and D5 of DAC Configuration register(Address = 1Bh) or using the LDAC register(Address = 1Ch).
Digital-to-Analog Section
INPUT REGISTER V REFAB Int VREF
BUF
REFERENCE BUFFER
GA IN MODE (GAIN=1 OR 2)
DAC REGISTER
RESISTOR STRING
VOUTA
OUTPUT BUFFER AMPLIFIER
Figure 7. Single DAC channel architecture
Resistor String
The resistor string section is shown in Figure 9. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
DAC Reference Inputs
There is a reference pin for each pair of DACs. The reference inputs are buffered but can also be individually configured as unbuffered.
VRE F-AB
The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin or the on-chip reference of 2.25 V provides the reference voltage for the corresponding DAC. Figure 7 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by: VREF * D VOUT = ---------2N where D=decimal equivalent of the binary code which is loaded to the DAC register; 0-255 for ADT7318 (8-Bits) 0-1023 for ADT7317 (10-Bits) 0-4095 for ADT7316 (12-Bits) N = DAC resolution.
2 . 25 V I nte rn a l V R EF
STRING DAC A STRING DAC B
Figure 8. DAC Reference Buffer Circuit
The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to headroom and footroom of the reference amplifier.
REV. PrN
-13-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
R R R TO OUTPUT AMPLIFIER
nominal value by the time 50ms has elasped then it is recommended that a measurement be taken on the VDD channel before a temperature measurement is taken.
TEMPERATURE SENSOR
R R
The ADT7316/7317/7318 contains a two-channel A to D converter with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. When the ADT7316/7317/7318 is operating normally, the A to D converter operates in a free-running mode. When in Round Robin mode the analog input multiplexer sequently selects the VDD input channel, on-chip temperature sensor to measure its internal temperature and then the external temperature sensor. These signals are digitized by the ADC and the results stored in the various Value Registers. The measured results are compared with the Internal and External, THIGH, TLOW limits. These temperature limits are stored in on-chip registers. If the temperature limits are not masked out then any out of limit comparisons generate flags that are stored in Interrupt Status 1 Register and one or more out-of limit results will cause the INTERRUPT output to pull either high or low depending on the output polarity setting. Theoretically, the temperature sensor and ADC can measure temperatures from -128oC to +127oC with a resolution of 0.25oC. However, temperatures outside TA are outside the guaranteed operating temperature range of the device. Temperature measurement from -128oC to +127oC is possible using an external sensor. Temperature measurement is initiated by three methods. The first method is applicable when the part is in single channel measurement mode. It uses an internal clock countdown of 20ms and then a conversion is preformed. The internal oscillator is the only circuit that's powered up between conversions and once it times out, every 20ms, a wake-up signal is sent to power-up the rest of the circuitry. A monostable is activated at the beginning of the wake-up signal to ensure that sufficient time is given to the power-up process. The monostable typically takes 4 s to time out. It then takes typically 25s for each conversion to be completed. The temperature is measured 16 times and internally averaged to reduce noise. The total time to measure a temperature channel is typically 400us (25us x 16). The new temperature value is loaded into the Temperature Value Register and ready for reading by the I2C or SPI interface. The user has the option of disabling the averaging by setting a bit (Bit 5) in the Control Configuration Register 2 (address 19h). The ADT7316/7317/ 7318 defaults on power-up with the averaging enabled. Temperature measurement is also initiated after every read or write to the part when the part is in single channel measurement mode. Once serial communication has started, any conversion in progress is stopped and the ADC reset. Conversion will start again immediately after the serial communication has finished. The temperature measurement proceeds normally as described above. The third method is applicable when the part is in round robin measurement mode. The part measures both the REV. PrN
Figure 9. Resistor String
If there is a buffered reference in the circuit , there is no need to use the on-chip buffers. In unbuffered mode the input impedance is still large at typically 90 k per reference input for 0-VREF output mode and 45 k for 0-2VREF output mode. The buffered/unbuffered option is controlled by the DAC Configuration Register (address 1Bh, see data register descriptions). The LDAC Configuration register controls the option to select between internal and external voltage references. The default setting is for external reference selected.
Output Amplifier
The output buffer amplifier is capable of generating output voltages to within 1mV of either rail. Its actual range depends on the value of VREF, GAIN and offset error. If a gain of 1 is selected (Bits 0-3 of DAC Configuration register = 0) the output range is 0.001 V to VREF. If a gain of 2 is selected (Bits 0-3 of DAC Configuration register = 1) the output range is 0.001 V to 2VREF. However because of clamping the maximum output is limited to VDD - 0.001V. The output to GND or The source can be seen amplifier is capable of driving a load of 2k VDD, in parallel with 500pF to GND or VDD. and sink capabilities of the output amplifier in the plot in TPC 11.
The slew rate is 0.7V/s with a half-scale settling time to +/-0.5 LSB (at 8 bits) of 6s.
FUNCTIONAL DESCRIPTION
POWER-UP TIME
On power-up it is important that no communication to the part is initiated until 200ms after Vcc has settled. During this 200ms the part is performing a calibration routine and any communication to the device will interrupt this routine and could cause erroneous temperature measurements. VDD must have settled to within 10% of it's final value after 50ms power-on time has elasped. Therefore once power is applied to the ADT7316/17/18, it can be addressed 250ms later. If it not possible to have VDD at it's
-14-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
internal and external temperature sensors as it cycles through all possible measurement channels. The two temperature channels are measured each time the part runs a round robin sequence. In round robin mode the part is continously measuring.
V DD MONITORING
6V 6.5 V 7V
ON-CHIP REFERENCE
11 0110 1101 11 1011 0110 11 1111 1111
36D 3B6 3FF
The ADT7316/17/18 also has the capability of monitoring it's own power supply. The part measures the voltage on it's VDD pin to a resolution of 10 bits. The resultant value is stored in two 8-bit registers, the two LSBs stored in register address 03h and the eight MSBs are stored in register address 06h. This allows the user to have the option of just doing a one byte read if 10-bit resolution is not important. The measured result is compared with VHIGH and VLOW limits. If the VDD interrupt is not masked out then any out of limit comparison generates a flag in Interrupt Status 2 Register and one or more out-of-limit results will cause the INTERRUPT output to pull either high or low depending on the output polarity setting. Measuring the voltage on the VDD pin is regarded as monitoring a channel. Therefore, along with the Internal and External temperature sensors the VDD voltage makes up the third and final monitoring channel. You can select the VDD channel for single channel measurement by setting Bit C4 = 1 and setting Bit 0 to Bit 2 to all 0's in Control Configuration 2 register. When measuring the VDD value the reference for the ADC is sourced from the Internal Reference. Table 2 shows the data format. As the max VCC voltage measurable is 7 V, internal scaling is performed on the VCC voltage to match the 2.25V internal reference value. Below is an example of how the transfer function works. VDD = 5 V ADC Reference = 2.25 V 1 LSB = ADC Reference / 2^10 = 2.25 / 1024 = 2.197mV Scale Factor = Fullscale VCC / ADC Reference = 7 / 2.25 = 3.11 Conversion Result = VDD / ((7/Scale Factor) x LSB size) = 5 / (3.11 x 2.197mV) = 2DBh
TABLE 2. VDD Data Format, VREF = 2.25V
The ADT7316/17/18 has an on-chip 1.2 V band-gap refernece which is gained up by a switched capacitor amplifier to give an output of 2.25 V. The amplifier is only powered up at the start of the conversion phase and is powered down at the end of conversion. On power-up the default mode is to have the internal reference selected as the reference for the DAC and ADC. The internal reference is always used when measuring the internal and external temperature sensors.
ROUND ROBIN MEASUREMENT
On power-up the ADT7316/17/18 goes into Round Robin mode but monitoring is disabled. Setting Bit C0 of Configuration Register 1 to a 1 enables conversions. It sequences through the three channels of VDD , Internal temperature sensor and External temperature sensor and takes a measurement from each. At intervals of tbd ms another measurement cycle is performed on all three channels. This method of taking a measurement on all three channels in one cycle is called Round Robin. Setting Bit 4 of Control Configuration 2 (address 19h) disables the Round Robin mode and in turn sets up the single channel mode. The single channel mode is where only one channel, eg. Internal temperature sensor, is measured in each conversion cycle. The time taken to monitor all channels will normally not be of interest, as the most recently measured value can be read at any time. For applications where the Round Robin time is important, it can be easily calculated. As mentioned previously a conversion on each temperature channel takes 25 us and on the VDD channel it takes 15 us. Each channel is measured 16 times and internally averaged to reduce noise. The total cycle time for voltage and temperature channels is therefore nominally :
(2 x 16 x 25) + (16 x 15) = 1.04 ms SINGLE CHANNEL MEASUREMENT
VDD Value
Digital Output Binary Hex 16E 1B7 200 249 292 2DB 324
2.5 V 3V 3.5 V 4V 4.5 V 5V 5.5 V REV. PrN
01 0110 1110 01 1011 0111 10 0000 0000 10 0100 1001 10 1001 0010 10 1101 1011 11 0010 0100
Setting C4 of Control Configuration 2 register enables the single channel mode and allows the ADT7316/17/18 to focus on one channel only. A channel is selected by writing to Bits 0:2 in register Control Configuration 2 register. For example, to select the VDD channel for monitoring write to the Control Configuration 2 register and set C4 to 1 (if not done so already), then write all 0's to bits 0 to 2 . All subsequent conversions will be done on the VDD channel only. To change the channel selection to the Internal temperature channel, write to the Control Configuration 2 register and set C0 = 1. When measuring in single channel mode there is a time delay of TBD us between each measurement. A measurement is also initiated after every read or write operation. -15-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
VDD I OPTIONAL CAPACITOR, UP TO 3nF MAX. CAN BE ADDED TO IMPROVE HIGH FREQUENCY NOISE REJECTION IN NOISY ENVIRONMENTS D+ C1 DLOWPASS FILTER fc = 65kHz BIAS DIODE V OUT+ TO ADC VO UTN xI I BIAS
REMOTE SENSING TR ANSISTOR (2N3906)
Figure 10. Signal Conditioning for External Diode temperature Sensors
MEASUREMENT METHOD
where: K is Boltzmann's constant q is charge on the carrier T is absolute temperature in Kelvins N is ratio of the two currents Figure 10 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor. If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input. We recommend that a 2N3906 be used as the external transistor. To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input. As the sensor is operating in a noisy environment, C1 is provided as a noise filter. See the section on layout considerations for more information on C1. To measure Vbe, the sensor is switched between operating currents of I and N x I. The resulting waveform is passed through a lowpass filter to remove noise, thence to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a DC voltage proportional to Vbe. This voltage is measured by the ADC to give a temperature output in 8-bit two's complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. -16- REV. PrN
INTERNAL TEMPERATURE MEASUREMENT The ADT7316/7317/7318 contains an on-chip bandgap temperature sensor, whose output is digitized by the onchip ADC. The temperature data is stored in the Internal Temperature Value Register. As both positive and negative temperatures can be measured, the temperature data is stored in two's complement format, as shown in Table 3. The thermal characteristics of the measurement sensor could change and therefore an offset is added to the measured value to enable the transfer function to match the thermal characteristics. This offset is added before the temperature data is stored. The offset value used is stored in the Internal Temperature Offset Register. EXTERNAL TEMPERATURE MEASUREMENT The ADT7316/7317/7318 can measure the temperature of one external diode sensor or diode-connected transistor. The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about -2mV/oC. Unfortunately, the absolute value of Vbe, varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass-production. The time taken to measure the external temperature can be reduced by setting C0 of Control Config. 3 register (1Ah). This increases the ADC clock speed from 1.4KHz to 22KHz but the analog filters on the D+ and D- input pins are switched off to accommodate the higher clock speeds. Running at the slower ADC speed, the time taken to measure the external temperature is TBD while on the fast ADC this time is reduced to TBD. The technique used in the ADT7316/7317/7318 is to measure the change in Vbe when the device is operated at two different currents. This is given by: Vbe = KT/q x ln(N)
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
V DD I NxI IBIAS
V OUT+ TO A DC VOUTINTERNAL SENSE TRA NSISTOR BIAS DIODE
Figure 11. Top Level Structure of Internal Temperature Sensor
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken: 1. Place the ADT7316/17/18 as close as possible remote sensing diode. Provided that the worst sources such as clock generators, data/address CRTs are avoided, this distance can be 4 to 8 to the noise buses and inches.
5. Place 0.1F bypass and 2200pF input filter capacitors close to the ADT7316/17/18. 6. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This will work up to about 6 to 12 feet. 7. For really long distances (up to 100 feet) use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND close to the ADT7316/17/18. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. 1 tance introduces about 0.5oC error.
TEMPERATURE VALUE FORMAT
2. Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. 3. Use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended.
GND 10 mil. 10 mil. D+ 10 mil. 10 mil. D10 mil. 10 mil. GND 10 mil.
series resis-
One LSB of the ADC corresponds to 0.25C. The ADC can theoretically measure a temperature span of 255 C. The internal temperature sensor is guaranteed to a low value limit of -40 C. It is possible to measure the full temperature span using the external temperature sensor. The temperature data format is shown in Tables 3. The result of the internal or external temperature measurements is stored in the temperature value registers, and is compared with limits programmed into the Internal or External High and Low Registers. TABLE 3. Temperature Data Format (Internal and External Temperature) Temperature Digital Output DB9..........DB0 -40 C 11 0110 0000
Figure 12. Arrangement of Signal Tracks
4. Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/ solder joints are used, make sure that they are in both the D+ and D- path and at the same temperature. Thermocouple effects should not be a major problem as 1oC corresponds to about 240V, and thermocouple voltages are about 3V/oC of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200mV. REV. PrN
-17-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
S/W Reset
INTERRUPT STATUS REGISTER 1 (TEMP and Ext. Diode Check)
Internal Temp
STATUS BITS
External Tem p
WATCHDOG LIMIT COMPA RISONS
INTERRUPT STATUS REGISTER 2 (V D D)
INTERRUPT MASK REGISTERS
VDD
INTERRUPT (Latched Output)
Diode Fault
STATUS BIT
Read Reset
CONTROL CONFIGURATION REGISTER 1
INTERRUPT ENABLE BIT
Figure 13. ADT7316/17/18 Interrupt Structure
-25 C -10 C -0.25 C 0 C +0.25 C +10 C +25 C +50 C +75 C +100 C +105 C +125 C
11 1001 1100 11 1101 1000 11 1111 1111 00 0000 0000 00 0000 0001 00 0010 1000 00 0110 0100 00 1100 1000 01 0010 1100 01 1001 0000 01 1010 0100 01 1111 0100
Interrupt Status 1 Register (address = 00h) and Interrupt Status 2 Register (address = 01h). One or more out-of limit results will cause the INTERRUPT output to pull either high or low depending on the output polarity setting. Figure 13 shows the interrupt structure for the ADT7316/ 17/18. It gives a block diagram representation of how the various measurement channels affect the INTERRUPT pin.
THERMAL VOLTAGE OUTPUT
Temperature Conversion Formula: 1. Positive Temperature = ADC Code/4 2. Negative Temperature = (ADC Code* - 512)/4
*DB9 is removed from the ADC Code
INTERRUPTS
The measured results from the inetrnal temperature sensor, external temperature sensor and the VDD pin are compared with the THIGH/VHIGH and TLOW/VLOW limits. These limits are stored in on-chip registers. Please note that the limit registers are 8 bits long while the conversion results are 10 bits long. If the limits are not masked out then any out of limit comparisons generate flags that are stored in
The ADT7316/17/18 has the capability of outputting a voltage that is proportional to temperature. DAC A output can be configured to reperesent the temperature of the internal sensor while DAC B output can be configured to reperesent the external temperature sensor. Bits 5 and 6 of Control Configuration 3 register select the temperature proportional output voltage. Each time a temperature measurement is taken the DAC output is updated. The output resolution ADT7318 is 8 bits with 1C change corresponding to one LSB change. The output resolution for the ADT7316 and ADT7317 is capable of 10 bits with 0.25C change corresponding to one LSB change. The default output resolution for the ADT7316 and ADT7317 is 8 bits. To increase this to 10 bits, set bit 1=1 of Control Configuration 3 register. The default output range is 0V-VREF and this can be increased to 0V-2VREF. Increasing the outout voltage span to 2VREF can be done by setting D0 = 1 for DAC A (Internal Temperature Sensor) and D1 = 1 for DAC B (External Temperature Sensor) in DAC Configuration register (address 1Bh). The output voltage is capable of tracking a max temperature range of -128C to +127C but the default setting is 40C to +127C. If the output voltage range is 0V-VREF -18- REV. PrN
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
(VREF = 2.25 V) then this corresponds to 0V representing 40C and 1.48V representing +127C. This of course will give an upper deadband between 1.48V and VREF. The Internal and External Analog Temperature Offset registers can be used to vary this upper deadband and consequently the temperature that 0V corresponds to. Tables 4 and 5 give examples of how this is done using a DAC output voltage span of VREF and 2VREF respectivily. Simply write in the temperature value, in 2's complement format, that you want 0V to start at. For example, if you are using the DAC A output and you want 0V to start at -40C then program D8h into the Internal Analog Temperature Offset register (address 21h). This is an 8-bit register and thus only has a temperature offset resolution of 1C for all device models. Use the following formulas to determine the value to program into the offset registers. Negative temperatures : Offset Register Code(d)* = (0V Temp) + 128
*D7 of Offset Register Code is set to 1 for negative temperatures.
0.75V 1V 1.12V 1.47V 1.5V 2V 2.25V 2.5V 2.75V 3V 3.25V 3.5V 3.75V 4V 4.25V 4.5V
+3 +17 +23 +43 +45 +73 +88 +102 +116 UDB* UDB* UDB* UDB* UDB* UDB* UDB*
-85 -71 -65 -45 -43 -15 0 +14 +28 +42 +56 +70 +85 +99 +113 +127
43 +57 +63 +83 +85 +113 +127 UDB* UDB* UDB* UDB* UDB* UDB* UDB* UDB* UDB*
Example : Offset Register Code(d) = (-40) + 128 = 88d = 58h
Since a negative temperature has been inputted into the equation, DB7 (MSB) of the Offset Register code is set to a 1. Therefore 58h becomes D8h.
58h + DB7(1) D8h
* Upper deadband has been reached. DAC output is not capable of increasing. Reference Figure 6.
The following equation is used to work out the various temperatures for the corresponding 8-bit DAC output :8-Bit Temp = (DAC O/P / 1 LSB) + ( 0V Temp)
Positive temperatures : Offset Register Code(d) = 0V Temp
Example : Offset Register Code (d) = 10d = 0Ah Table 4. Thermal Voltage Output (0V-VREF)
For example, if the output is 1.5V, VREF = 2.25 V, 8-bit DAC has an LSB size = 2.25V/255 = 8.82x10-3, and 0V Temp is at -128C then the resultant temperature works out to be :(1.5 /8.82x10-3) + (-128) = +42C
O/P Voltage 0V 0.5V 1V 1.12V 1.47V 1.5V 2V 2.25V
Default C -40 +17 +73 +87 +127 UDB* UDB* UDB*
Max C -128 -71 -15 -1 +39 +42 +99 +127
Sample C 0 +56 +113 +127 UDB* UDB* UDB* UDB* Figure 14 shows a graph of DAC output vs temperature for a VREF = 2.25 V. The following equation is used to work out the various temperatures for the corresponding 10-bit DAC output :10-Bit Temp = ((DAC O/P / 1 LSB)x0.25) + ( 0V Temp)
For example, if the output is 0.4991V, VREF = 2.25 V, 10bit DAC has an LSB size = 2.25V/1024 = 2.197x10-3, and 0V Temp is at -40C then the resultant temperature works out to be :((0.4991 /2.197x10-3)x0.25) + (-40) = +16.75C
* Upper deadband has been reached. DAC output is not capable of increasing. Reference Figure 6.
Table 5.
Thermal Voltage Output, (0V-2VREF)
O/P Voltage 0V 0.25V 0.5V REV. PrN
Default C -40 -26 +12
Max C -128 -114 -100
Sample C 0 14 +28 -19-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
2nd READ COMMAND
2.25 2.10 1.95 1.80 DAC OUTPUT (V) 1.65 1.50 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0.30 0.15 0.00 10 0 V = -128'C 0 V = -40'C
MSB REGISTER
OUTPUT DATA
UNLOCK ASSOCIATED MSB REGISTERS
Figure 16. Phase 2 of 10-Bit Read
If an MSB register is read first, it's corresponding LSB register is not locked thus leaving the user with the option of just reading back 8 bits (MSB) of a 10-bit conversion result. Reading an MSB register first does not lock up other MSB registers and likewise reading an LSB register first does not lock up other LSB registers.
Table 6. List of ADT7316/7317/7318 Registers
RD/WR
0 V = 0'C
Name
Power-on Default
Address 00h Interrupt Status 1 Interrupt Status 2 RESERVED Internal Temp & VDD LSBs External Temp LSBs RESERVED VDD MSBs Internal Temperature MSBs External Temp MSBs
00h 00h
-128 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
20
30
40
50
60
70
80
90 100 110 120 127
Temperature ('C)
01h 02h
Figure 14. DAC Output vs Temperature, VREF = 2.25 V
ADT7316/7317/7318 REGISTERS
03h 04h 05h 06h 07h 08h
00h 00h
The ADT7316/17/18 contains registers that are used to store the results of external and internal temperature measurements, VDD value measurements, high and low temperature and supply voltage limits, set output DAC voltage levels, configure multipurpose pins and generally control the device. A description of these registers follows. The register map is divided into registers of 8-bits long. Each register has it's own indvidual address but some consist of data that is linked with other registers. These registers hold the 10-bit conversion results of measurements taken on the Temperature and VDD channels. For example, the 8 MSBs of the VDD measurement are stored in register address 06h while the 2 LSBs are stored in register address 03h. The link involved between these types of registers is that when the LSB register is read first then the MSB registers associated with that LSB register are locked to prevent any updates. To unlock these MSB registers the user has only to read any one of them, which will have the affect of unlocking all previously locked MSB registers. So for the example given above if register 03h was read first then MSB registers 06h and 07h would be locked to prevent any updates to them. If register 06h was read then this register and register 07h would be subsequently unlocked.
1st READ COMMAND LSB REGISTER OUTPUT DATA
00h 00h 00h
09h-0Fh
RESERVED
10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch
DAC A LSBs (ADT7316/17 only) DAC A MSBs DAC B LSBs (ADT7316/17 only) DAC B MSBs DAC C LSBs (ADT7316/17 only) DAC C MSBs DAC D LSBs (ADT7316/17 only) DAC D MSBs Control CONFIG 1 Control CONFIG 2 Control CONFIG 3 DAC CONFIG LDAC CONFIG Interrupt Mask 1 Interrput Mask 2 Internal Temp Offset External Temp Offset Internal Analog Temp Offset
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h D8h REV. PrN
LOCK ASSOCIATED MSB REGISTERS
1Dh 1Eh 1Fh 20h 21h -20-
Figure 15. Phase 1 of 10-Bit Read
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
22h 23h 24h 25h 26h 27h 28h External Analog Temp Offset VDD VHIGH Limit VDD VLOW Limit Internal THIGH Limit Internal TLOW Limit External THIGH External TLOW RESERVED D8h C9h 62h 64h C9h FFh 00h
INTERNAL TEMPERATURE VALUE/VDD VALUE REGISTER LSBs (Read only) [Add. = 03h]
Bit D4
Function 1 when VDD value exceeds corrosponding VHIGH and VLOW limits
29h-4CH
This Internal Temperature Value and VDD Value Register is a 8-bit read-only register. It stores the two LSBs of the 10-bit temperature reading from the internal temperature sensor and also the two LSBs of the 10-bit supply voltage reading.
Table 9. Internal Temp/VDD LSBs
4Dh 4Eh 4Fh
Device ID Manufacturer's ID Silicon Revision
01h/05h/09h 41h 00h D7 N/A N/A D6 N/A N/A
D5 N/A N/A
D4 N/A N/A
D3 V1 0*
D2 LSB 0*
D1 T1 0*
D0 LSB 0*
50h-FFh
RESERVED
*Default settings at Power-up.
Interrupt Status 1 Register (Read only) [Add. = 00h]
Bit D0 D1 D2 D3
Function LSB of Internal Temperature Value B1 of Internal Temperature Value LSB of VDD Value B1 of VDD Value
This 8-bit read only register reflects the status of some of the interrupts that can cause the INTERRUPT pin to go active. This register is reset by a read operation or by a software reset.
Table 7. Interrupt Status 1 Register
D7 N/A
D6 N/A
D5 N/A
D4 0*
D3 0*
D2 0*
D1 0*
D0 0*
EXTERNAL TEMPERATURE VALUE REGISTER LSBS (Read only) [Add. = 04h]
*Default settings at Power-up.
Bit D0 D1 D2 D3 D4
Function 1 when Internal Temp Value exceeds THIGH limit 1 when Internal Temp Value exceeds TLOW limit 1 when External Temp Value exceeds THIGH limit 1 when External Temp Value exceeds TLOW limit 1 indicates a fault (open or short) for the external temperature sensor.
This External Temperature Value is a 8-bit read-only register. It stores the two LSBs of the 10-bit temperature reading from the external temperature sensor.
Table 10. External Temperature LSBs
D7 N/A N/A
D6 N/A N/A
D5 N/A N/A
D4 N/A N/A
D3 N/A N/A
D2 N/A N/A
D1 T1 0*
D0 LSB 0*
*Default settings at Power-up.
Interrupt Status 2 Register (Read only) [Add. = 01h]
Bit D0 D1
Function LSB of External Temperature Value B1 of External Temperature Value
This 8-bit read only register reflects the status of the VDD interrupt that can cause the INTERRUPT pin to go active. This register is reset by a read operation or by a software reset.
Table 8. Interrupt Status 1 Register
VDD VALUE REGISTER MSBS (Read only) [Add. = 06h]
D7 N/A
D6 N/A
D5 N/A
D4 0*
D3 N/A
D2 N/A
D1 N/A
D0 N/A
This 8-bit read only register stores the supply voltage value. The 8 MSBs of the 10-bit value are stored in this register.
Table 11. VDD Value MSBs
*Default settings at Power-up.
REV. PrN
-21-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
D7 V9 0* D6 V8 0* D5 V7 0* D4 V6 0* D3 V5 0* D2 V4 0* D1 V3 0* D0 V2 0*
DAC A REGISTER MSBS (Read/Write) [Add. = 11h]
*Default settings at Power-up.
This 8-bit read/write register contains the 8 MSBs of the DAC A word. The value in this register is combined with the value in the DAC A Register LSBs and converted to an analog voltage on the VOUTA pin. On power-up the voltage output on the VOUTA pin is 0 V.
Table 16. DAC A MSBs
INTERNAL TEMPERATURE VALUE REGISTER MSBS (Read only) [Add. = 07h]
D7 MSB 0*
D6 B8 0*
D5 B7 0*
D4 B6 0*
D3 B5 0*
D2 B4 0*
D1 B3 0*
D0 B2 0*
This 8-bit read only register stores the Internal Temperature value from the internal temperature sensor in twos complement format. The 8 MSBs of the 10-bit value are stored in this register.
Table 12. Internal Temperature Value MSBs
*Default settings at Power-up.
DAC B REGISTER LSBS (Read/Write) [Add. = 12h]
D7 T9 0*
D6 T8 0*
D5 T7 0*
D4 T6 0*
D3 T5 0*
D2 T4 0*
D1 T3 0*
D0 T2 0*
*Default settings at Power-up.
This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/7317 DAC B word respectivily. The value in this register is combined with the value in the DAC B Register MSBs and converted to an analog voltage on the VOUTB pin. On power-up the voltage output on the VOUTB pin is 0 V.
Table 17. DAC B (ADT7316) LSBs
EXTERNAL TEMPERATURE VALUE REGISTER MSBS (Read only) [Add. = 08h]
This 8-bit read only register stores the External Temperature value from the external temperature sensor in twos complement format. The 8 MSBs of the 10-bit value are stored in this register.
Table 13. External Temperature Value MSBs
D7 B3 0*
D6 B2 0*
D5 B1 0*
D4 LSB 0*
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
*Default settings at Power-up.
D7 T9 0*
D6 T8 0*
D5 T7 0*
D4 T6 0*
D3 T5 0*
D2 T4 0*
D1 T3 0*
D0 T2 0* D7 B2 0* D6 LSB 0*
Table 18. DAC B (ADT7317) LSBs
D5 N/A N/A
D4 N/A N/A
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
*Default settings at Power-up.
DAC A REGISTER LSBS (Read/Write) [Add. = 10h]
*Default settings at Power-up.
This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/7317 DAC A word respectivily. The value in this register is combined with the value in the DAC A Register MSBs and converted to an analog voltage on the VOUTA pin. On power-up the voltage output on the VOUTA pin is 0 V.
Table 14. DAC A (ADT7316) LSBs
DAC B REGISTER MSBS (Read/Write) [Add. = 13h]
This 8-bit read/write register contains the 8 MSBs of the DAC B word. The value in this register is combined with the value in the DAC B Register LSBs and converted to an analog voltage on the VOUTB pin. On power-up the voltage output on the VOUTB pin is 0 V.
Table 19. DAC B MSBs
D7 B3 0*
D6 B2 0*
D5 B1 0*
D4 LSB 0*
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A D7 MSB 0* D6 B8 0* D5 B7 0* D4 B6 0* D3 B5 0* D2 B4 0* D1 B3 0* D0 B2 0*
*Default settings at Power-up.
*Default settings at Power-up.
Table 15. DAC A (ADT7317) LSBs DAC C REGISTER LSBS (Read/Write) [Add. = 14h]
D7 B2 0*
D6 LSB 0*
D5 N/A N/A
D4 N/A N/A
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
*Default settings at Power-up.
This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/7317 DAC C word respectivily. The value in this register is combined with the value in the DAC C Register MSBs and converted to an analog voltage on the VOUTC pin. On power-up the voltage output on the VOUTC pin is 0 V. -22- REV. PrN
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
Table 20. DAC C (ADT7316) LSBs Table 25. DAC D MSBs
D7 B3 0*
D6 B2 0*
D5 B1 0*
D4 LSB 0*
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
D7 MSB 0*
D6 B8 0*
D5 B7 0*
D4 B6 0*
D3 B5 0*
D2 B4 0*
D1 B3 0*
D0 B2 0*
*Default settings at Power-up.
*Default settings at Power-up.
Table 21. DAC C (ADT7317) LSBs
CONTROL CONFIGURATION 1 REGISTER (Read/ Write) [Add. = 18h]
D7 B2 0*
D6 LSB 0*
D5 N/A N/A
D4 N/A N/A
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18.
Table 26. Control Configuration 1
*Default settings at Power-up.
DAC C REGISTER MSBS (Read/Write) [Add. = 15h]
D7 PD 0*
D6 C6 0*
D5 C5 0*
D4 C4 0*
D3 C3 0*
D2 C2 0*
D1 C1 0*
D0 C0 0*
This 8-bit read/write register contains the 8 MSBs of the DAC C word. The value in this register is combined with the value in the DAC C Register LSBs and converted to an analog voltage on the VOUTC pin. On power-up the voltage output on the VOUTC pin is 0 V.
Table 22. DAC C MSBs
*Default settings at Power-up.
Bit C0 D7 MSB 0* D6 B8 0* D5 B7 0* D4 B6 0* D3 B5 0* D2 B4 0* D1 B3 0* D0 B2 0* C1:4 C5 C6
Function This bit enables/disables conversions in Round Robin mode. ADT7316/17/18 powers up in Round Robin mode but monitoring is not initiated until this bit is set. Default = 0. 0 = Disable Round Robin monitoring. 1 = Enable Round Robin monitoring. RESERVED. Only write 0's. 0 1 Enable INTERRUPT Disable INTERRUPT
*Default settings at Power-up.
DAC D REGISTER LSBS (Read/Write) [Add. = 16h]
This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/7317 DAC D word respectivily. The value in this register is combined with the value in the DAC D Register MSBs and converted to an analog voltage on the VOUTD pin. On power-up the voltage output on the VOUTD pin is 0 V.
Table 23. DAC D (ADT7316) LSBs
Configures INTERRUPT output polarity. 0 Active low 1 Active High Power-down Bit. Setting this bit to 1 puts the ADT7316/17/18 into standby mode. In this mode both ADC and DACs are fully powered down, but serial interface is still operational. To power up the part again just write 0 to this bit.
C7
D7 B3 0*
D6 B2 0*
D5 B1 0*
D4 LSB 0*
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
*Default settings at Power-up.
CONTROL CONFIGURATION 2 REGISTER (Read/ Write) [Add. = 19h]
Table 24. DAC D (ADT7317) LSBs
D7 B2 0*
D6 LSB 0*
D5 N/A N/A
D4 N/A N/A
D3 N/A N/A
D2 N/A N/A
D1 N/A N/A
D0 N/A N/A
This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18.
Table 27. Control Configuration 2
D7 C7 0*
D6 C6 0*
D5 C5 0*
D4 C4 0*
D3 C3 0*
D2 C2 0*
D1 C1 0*
D0 C0 0*
*Default settings at Power-up.
DAC D REGISTER MSBS (Read/Write) [Add. = 17h]
This 8-bit read/write register contains the 8 MSBs of the DAC D word. The value in this register is combined with the value in the DAC D Register LSBs and converted to an analog voltage on the VOUTD pin. On power-up the voltage output on the VOUTD pin is 0 V. REV. PrN
*Default settings at Power-up.
Bit
Function
-23-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
C2:0 In single channel mode these bits select between VDD, the internal temperature sensor and the external temperature sensor for conversion. Default is VDD. 000 = VDD 001 = Internal Temperature Sensor. 010 = External Temperature Sensor 011 - 111 = RESERVED RESERVED Selects between single channel and Round Robin conversion cycle. Default is Round Robin. 0 = Round Robin. 1 = Single Channel. Default condition is to average every measurement on all channels 16 times. This bit disables this averaging. Channels consist of temperature, analog inputs and VDD. 0 = Enable averaging. 1 = Disable averaging. SMBus timeout on the serial clock puts a max limit on the pulse width of the clock. Ensures that a fault on the master SCL does not lock up the SDA line. 0 = Disable SMBus Timeout. 1 = Enable SMBus Timeout. Software Reset. Setting this bit to a 1 causes a software reset. All registers and DAC outputs will reset to their default settings. C6 C3 0 = LDAC pin controls updating of DAC outputs. 1 = DAC Configration register and LDAC Configuration register control updating of DAC outputs. RESERVED. Only write 0. Setting this bit selects DAC A voltage output to be proportional to the internal temperature measurement. Setting this bit selects DAC B voltage output to be proportional to the external temperature measurement. RESERVED. Only write 0.
C4 C5
C3 C4
C5
C7
DAC CONFIGURATION REGISTER (Read/Write) [Add. = 1Bh]
C6
This configuration register is an 8-bit read/write register that is used to control the output ranges of all four DACs and also to control the loading of the DAC registers if the LDAC pin is disabled (bit C3 = 1, Control Configuration 3 register).
Table 29. DAC Configuration
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
C7
*Default settings at Power-up.
CONTROL CONFIGURATION 3 REGISTER (Read/ Write) [Add. = 1Ah]
Bit D0
Function Selects the output range of DAC A. 0 = 0 V to VREF. 1 = 0 V to 2VREF. Selects the output range of DAC B. 0 = 0 V to VREF. 1 = 0 V to 2VREF. Selects the output range of DAC C. 0 = 0 V to VREF. 1 = 0 V to 2VREF. Selects the output range of DAC D. 0 = 0 V to VREF. 1 = 0 V to 2VREF. 00 MSB write to any DAC register generates LDAC command which updates that DAC only. MSB write to DAC B or DAC D register generates LDAC command which updates DACs A, B or DACs C, D. MSB write to DAC D register generates LDAC command which updates all 4 DACs. LDAC command generated from LDAC register.
This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/17/18.
Table 28. Control Configuration 3
D1 D0 C0 0* D3 D2
D7 C7 0*
D6 C6 0*
D5 C5 0*
D4 C4 0*
D3 C3 0*
D2 C2 0*
D1 C1 0*
*Default settings at Power-up.
Bit C0
Function Selects between fast and normal ADC conversion speeds for all three monitoring channels. 0 = ADC clock at 1.4 KHz. 1 = ADC clock at 22.5 KHz. On the ADT7316 and ADT7317, this bit selects between 8 bits and 10 bits DAC output resolution on the Thermal Voltage Output feature. Default = 8 bits. This bit has no affect on the ADT7318 output as this part has only an 8-bit DAC. In the ADT7318 case, write 0 to this bit. 0 = 8 bits resolution. 1 = 10 bits resolution. RESERVED. Only write 0's. -24- D5:D4
01
C1
10
11
C2
REV. PrN
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
D6 Setting this bit allows the external VREF to bypass the reference buffer when supplying DACs A and B. Setting this bit allows the external VREF to bypass the reference buffer when supplying DACs C and D.
*Default settings at Power-up.
Bit D0 D1 D2 D3 D4 D5:D7
Function 0 = Enable internal THIGH interrupt. 1 = Disable internal THIGH interrupt. 0 = Enable internal TLOW interrupt. 1 = Disable internal TLOW interrupt. 0 = Enable external THIGH interrupt. 1 = Disable external THIGH interrupt. 0 = Enable external Tlow interrupt. 1 = Disable external Tlow interrupt. 0 = Enable external temperature fault interrupt. 1 = Disable external temperature fault interrupt. RESERVED. Only write 0's.
D7
LDAC CONFIGURATION REGISTER (Write only) [Add. = 1Ch]
This configuration register is an 8-bit write register that is used to control the updating of the quad DAC outputs if the LDAC pin is disabled and Bits 4 and 5 of DAC Configuration register are both set to 1. Also selects VREF for all four DACs. All of the bits in this register are self clearing i.e. reading back from this register will always give 0's.
Table 30. LDAC Configuration
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
INTERRUPT MASK 2 REGISTER (Read/Write) [Add. = 1Eh]
This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can can cause the INTERRUPT pin to go active.
Table 32. Interrupt Mask 2
*Default settings at Power-up.
Bit D0 D1 D2 D3 D4
Function Writing a 1 to this bit will generate the LDAC command to update DAC A output only. Writing a 1 to this bit will generate the LDAC command to update DAC B output only. Writing a 1 to this bit will generate the LDAC command to update DAC C output only. Writing a 1 to this bit will generate the LDAC command to update DAC D output only. Selects either internal or external VREFAB for DACs A and B. 0 = External VREF 1 = Internal VREF Selects either internal or external VREFCD for DACs C and D. 0 = External VREF 1 = Internal VREF RESERVED. Only write 0's.
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
Bit D0:D3 D4 D5:D7
Function RESERVED. Only write 0's. 0 = Enable VDD interrupts. 1 = Disable VDD interrupts. RESERVED. Only write 0's.
D5
INTERNAL TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 1Fh]
D6:D7
INTERRUPT MASK 1 REGISTER (Read/Write) [Add. = 1Dh]
This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can can cause the INTERRUPT pin to go active.
Table 31. Interrupt Mask 1
This register contains the Offset Value for the Internal Temperature Channel. A 2's complement number can be written to this register which is then 'added' to the measured result before it is stored or compared to limits. In this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. As it is an 8-bit register the temperature resolution is 1oC.
Table 33. Internal Temperature Offset
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
REV. PrN
-25-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
EXTERNAL TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 20h]
D7 D7 1*
D6 D6 1*
D5 D5 0*
D4 D4 1*
D3 D3 1*
D2 D2 0*
D1 D1 0*
D0 D0 0*
This register contains the Offset Value for the Internal Temperature Channel. A 2's complement number can be written to this register which is then 'added' to the measured result before it is stored or compared to limits. In this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. As it is an 8-bit register the temperature resolution is 1oC.
Table 34. External Temperature Offset
*Default settings at Power-up.
VDD VHIGH LIMIT REGISTER (Read/Write) [Add. = 23h]
This limit register is an 8-bit read/write register which stores the VDD upper limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured VDD value has to be greater than the value in this register. Default value is 5.5 V.
Table 37. VDD VHIGH Limit
D7 D7 0*
D6 D6 0*
D5 D5 0*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 0*
D0 D0 0*
D7 D7 1*
D6 D6 1*
D5 D5 0*
D4 D4 0*
D3 D3 1*
D2 D2 0*
D1 D1 0*
D0 D0 1*
*Default settings at Power-up.
*Default settings at Power-up.
INTERNAL ANALOG TEMPERATURE OFFSET REGISTER (Read/Write) [Add. = 21h]
VDD VLOW LIMIT REGISTER (Read/Write) [Add. = 24h]
This register contains the Offset Value for the Internal Thermal Voltage output. A 2's complement number can be written to this register which is then 'added' to the measured result before it is converted by DAC A. Varying the value in this register has the affect of varying the temperature span. For example, the output voltage can represent a temperature span of -128oC to +127oC or even 0oC to +127oC. In essence this register changes the position of 0V on the temperature scale. Anything other than -128oC to +127oC will produce an upper deadband on the DAC A output. As it is an 8-bit register the temperature resolution is 1oC. Default value is -40oC.
Table 35. Internal Analog Temperature Offset
This limit register is an 8-bit read/write register which stores the VDD lower limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured VDD value has to be less than the value in this register. Default value is 2.7 V.
Table 38. VDD VHIGH Limit
D7 D7 0*
D6 D6 1*
D5 D5 1*
D4 D4 0*
D3 D3 0*
D2 D2 0*
D1 D1 1*
D0 D0 0*
*Default settings at Power-up.
INTERNAL THIGH LIMIT REGISTER (Read/Write) [Add. = 25h]
D7 D7 1*
D6 D6 1*
D5 D5 0*
D4 D4 1*
D3 D3 1*
D2 D2 0*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
EXTERNAL ANALOG TEMPERATURE OFFSET REGISTER (Read/Write)[Add. = 22h]
This limit register is an 8-bit read/write register which stores the 2's complement of the internal temperature upper limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured Internal Temperature Value has to be greater than the value in this register. As it is an 8-bit register the temperature resolution is 1oC. Default value is +100oC.
Table 39. Internal THIGH Limit
This register contains the Offset Value for the External Thermal Voltage output. A 2's complement number can be written to this register which is then 'added' to the measured result before it is converted by DAC B. Varying the value in this register has the affect of varying the temperature span. For example, the output voltage can represent a temperature span of -128oC to +127oC or even 0oC to +127oC. In essence this register changes the position of 0V on the temperature scale. Anything other than -128oC to +127oC will produce an upper deadband on the DAC B output. As it is an 8-bit register the temperature resolution is 1oC. Default value is -40oC.
Table 36. External Analog Temperature Offset
D7 D7 0*
D6 D6 1*
D5 D5 1*
D4 D4 0*
D3 D3 0*
D2 D2 1*
D1 D1 0*
D0 D0 0*
*Default settings at Power-up.
INTERNAL TLOW LIMIT REGISTER (Read/Write) [Add. 26h]
This limit register is an 8-bit read/write register which stores the 2's complement of the internal temperature lower limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured Internal Temperature Value has to be more REV. PrN
-26-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
negative than the value in this register. As it is an 8-bit register the temperature resolution is 1oC. Default value is -55 oC.
Table 40. Internal TLOW Limit Table 41. External THIGH Limit
D7 D7 1*
D6 D6 1*
D5 D5 1*
D4 D4 1*
D3 D3 1*
D2 D2 1*
D1 D1 1*
D0 D0 1*
D7 D7 1*
D6 D6 1*
D5 D5 0*
D4 D4 0*
D3 D3 1*
D2 D2 0*
D1 D1 0*
D0 D0 1*
*Default settings at Power-up.
EXTERNAL TLOW LIMIT REGISTER (Read/Write) [Add. = 28h]
*Default settings at Power-up.
EXTERNAL THIGH LIMIT REGISTER (Read/Write) [Add. = 27h]
If pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write register which stores the 2's complement of the external temperature upper limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured External Temperature Value has to be greater than the value in this register. As it is an 8-bit register the temperature resolution is 1oC.
If pins 7 and 8 are configured for the external temperature sensor then this limit register is an 8-bit read/write register which stores the 2's complement of the external temperature lower limit that will cause an interrupt and activate the INTERRUPT output (if enabled). For this to happen the measured External Temperature Value has to be more negative than the value in this register. As it is an 8-bit register the temperature resolution is 1oC.
Table 42. External TLOW Limit
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
1 SCL
9
1
9
SDA START BY MASTER
1
0
0
1
A2
A1
A0
R/9 ACK. BY ADT7316/17/18
P7
P6
P5
P4
P3
P2
P1
P0 ACK. BY ADT7316/17/18 STOP BY MASTER
FR AME 1 SERIAL BUS ADDRESS B YTE
FRAME 2 ADDRESS POINTER REGISTER BYTE
Figure 17. I2C - Writing to the Address Pointer Register to select a register for a subsequent Read operation
1 SCL
9
1
9
SDA START BY MASTER
1
0
0
1
A2
A1
A0
R/9 ACK. BY ADT7316/17/18
P7
P6
P5
P4
P3
P2
P1
P0 ACK. BY ADT7316/17/18
FRAME 1 SERIAL BUS ADDRESS B YTE 1 SCL (CONTINUED)
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7316/17/18 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 18. I2C - Writing to the Address Pointer Register followed by a single byte of data to the selected register
REV. PrN
-27-
PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at Power-up.
ADT7316/17/18 version number. The ADT7316/17/18's version number is 0000b.
ADT7316/7317/7318 SERIAL INTERFACE
DEVICE ID REGISTER (READ ONLY) [ADD. = 4DH]
This 8-bit read only register indicates which part the device is in the model range. ADT7316 = 01h, ADT7317 = 05h and ADT7318 = 09h.
MANUFACTURER'S ID REGISTER (Read only) [Add. = 4Eh]
There are two serial interfaces that can be used on this part, I2C and SPI. A valid serial communication protocol selects the type of interface.
SERIAL INTERFACE SELECTION
This register contains the manufacturers identification number. ADI's is 41h.
SILICON REVISION REGISTER (Read only) [Add. = 4Fh]
This register is divided into the four lsbs representing the Stepping and the four msbs representing the Version. The Stepping contains the manufacturers code for minor revisions or steppings to the silicon. The Version is the
The CS line controls the selection between I2C and SPI. If CS is held high during a valid I2C communication then the serial interface selects the I2C mode once the correct serial bus address has been recognised. To set the interface to SPI mode the CS line must be low during a valid SPI communication. This will cause the interface to select the SPI mode once the correct read or write command has been recognised. As per most SPI standards the CS line must be low during every SPI communication to the ADT7316/17/18 and high all other times.
1 SCL
9
1
9
SDA START BY MASTER
1
0
0
1
A2
A1
A0
R/9
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY MASTER STOP BY MASTER
ACK. BY ADT7316/17/18 FRAME 1 SERIAL BUS ADDRESS BYTE
FRA ME 2 SINGL E DATA BYTE FROM ADT7316/17/18
Figure 19. I2C - Reading a single byte of data from a selected register
CS 1 SCL K 8 8
1
DIN START
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED) 1 SCL K (CONTINUED) 8
DIN (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
Figure 20. SPI - Writing to the Address Pointer Register followed by a single byte of data to the selected register
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
The following sections describe in detail how to use these interfaces.
I2C SERIAL INTERFACE
data to be read from or written to it. If the R/W bit is a 0 then the master will write to the slave device. If the R/W bit is a 1 the master will read from the slave device. 2. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will pull the data line high during the low period before the 9th clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
WRITING TO THE ADT7316/7317/7318
Like all I2 C-compatible devices, the ADT7316/7317/7318 has an 7-bit serial address. The four MSBs of this address for the ADT7316/7317/7318 are set to 1001. The three LSBs are set by pin 11, ADD. The ADD pin can be configured three ways to give three different address options; low, floating and high. Setting the ADD pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. There is a programmable SMBus timout. When this is enabled the SMBus will timeout after 25 ms of no activity. To enable it, set Bit 6 of Control Configuration 2 register. The power-up default is with the SMBus timeout disabled. The ADT7316/17/18 supports SMBus Packet Error Checking (PEC) and it's use is optional. It is triggered by supplying the extra clocks for the PEC byte. The PEC is calculated using CRC-8. The Frame Clock Sequence (FCS) conforms to CRC-8 by the polynominal :
C(x) = x8 + x2 + x1 + 1
Consult SMBus specification for more information. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA whilst the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit. All other devices on the bus now remain idle whilst the selected device waits for
Depending on the register being written to, there are two different writes for the ADT7316/7317/7318. It is not possible to do a block write to this part i.e no I2C autoincrement.
Writing to the Address Pointer Register for a subsequent read.
In order to read data from a particular register, the Address Pointer Register must contain the address of that register. If it does not, the correct address must be written to the Address Pointer Register by performing a singlebyte write operation, as shown in Figure 17. The write operation consists of the serial bus address followed by the address pointer byte. No data is written to any of the data registers. A read operation is then performed to read the register.
CS 1 SCL K 8 8
1
DIN START
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0 STOP
WRITE COMMAND
REGISTER ADDRESS
Figure 21. SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
Writing data to a Register.
All registers are 8-bit registers so only one byte of data can be written to each register. Writing a single byte of data to one of these Read/Write registers consists of the serial bus address, the data register address written to the Address Pointer Register, followed by the data byte written to the selected data register. This is illustrated in Figure 18. To write to a different register, another START or repeated START is required. If more than one byte of data is sent in one communication operation, the addressed register will be repeately loaded until the last data byte has been sent.
READING DATA FROM THE ADT7316/7317/7318
having been set up by a single byte write operation to the Address Pointer Register. If you want to read from another register then you will have to write to the Address Pointer Register again to set up the relevant register address. Thus block reads are not possible i.e. no I2C auto-increment.
SPI SERIAL INTERFACE
Reading data from the ADT7516/7517/7518 is done in a one byte operation. Reading back the contents of a register is shown in Figure 19. The register address previously
The SPI serial interface of the ADT7316/7317/7318 consists of four wires, CS, SCLK, DIN and DOUT. The CS is used to select the device when more than one device is connected to the serial clock and data lines. The SCLK is used to clock data in and out of the part. The DIN line is used to write to the registers and the DOUT line is used to read data back from the registers. The part operates in a slave mode and requires an externally applied serial clock to the SCLK input. The serial
CS 1 SCLK 8 8
1
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT START
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0 STOP
READ COMMAND
DATA BYTE 1
Figure 22. SPI - Reading a single byte of data from a selected register
CS 1 SCLK 8 8
1
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT START
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
READ COMMAND
DATA BYTE 1
CS (CONTINUED) 1 SCLK (CONTINUED) 8
DIN (CONTINUED) DOUT (CONTINUED)
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0 STOP
DATA BYTE 2
Figure 23. SPI - Reading a two bytes of data from two sequential registers
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. There are two types of serial operations, a read and a write. Command words are used to distinguish between a read and a write operation. These command words are given in Table 43. Address auto-increment is possible in SPI mode
Table 43. SPI COMMAND WORDS
The INTERRUPT pin has an open-drain configuration which allows the outputs of several devices to be wiredAND together when the INTERRUPT pin is active low. Use D6 of the Control Configuration 1 Register to set the active polarity of the INTERRUPT output. The power-up default is active low. The INTERRUPT function can be disabled or enabled by setting D5 of Control Configuration 1 Register to a 1 or 0 respectively. The INTERRUPT output becomes active when either the Internal Temperature Value, the External Temperature Value or the VDD Value exceed the values in their corresponding THIGH/VHIGH or TLOW/VLOW Registers. The INTERRUPT output goes inactive again when a conversion result has the measured value back within the trip limits. The INTERRUPT output requires an external pull-up resistor. This can be connected to a voltage different from VDD provided the maximum voltage rating of the INTERRUPT output pin is not exceeded. The value of the pullup resistor depends on the application, but should be as large enough to avoid excessive sink currents at the INTERRUPT output, which can heat the chip and affect the temperature reading.
WRITE 90h (1001 0000)
Write Operation
READ 91h (1001 0001)
Figures 20 and 21 show the timing diagrams for a write operation to the ADT7316/7317/7318. Data is clocked into the registers on the rising edge of SCLK. When the CS line is high the DIN and DOUT lines are in threestate mode. Only when the CS goes from a high to a low does the part accept any data on the DIN line. In SPI mode the Address Pointer Register is capable of autoincrementing to the next register in the register map without having to load the Address Pointer register each time. In Figure 20 the register address portion of the diagram gives the first register that will be written to. Subsequent data bytes will be written into sequential writable registers. Thus after each data byte has been written into a register, the Address Pointer Register auto increments it's value to the next available register. The Address Pointer Register will auto-increment from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh.
Read Operation
Figures 22 and 23 show the timing diagrams necessary to accomplish correct read operations. To read back from a register you first have to write to the Address Pointer Register with the address of the register you wish to read from. This operation is shown in Figure 21. Figure 22 shows the procedure for reading back a single byte of data. The read command is first sent to the part during the first 8 clock cycles, during the following 8 clock cycles the data contained in the register selected by the Address Pointer register is outputted onto the DOUT line. Data is outputted onto the DOUT line on the falling edge of SCLK. Figure 23 shows the procedure when reading data from two sequential registers. Multiple data reads are possible in SPI interface mode as the Address Pointer Register is auto-incremental. The Address Pointer Register will auto-increment from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh.
SMBUS/SPI INTERRUPT
The ADT7316/17/18 INTERRUPT output is an interrupt line for devices that want to trade their ability to master for an extra pin. The ADT7316/17/18 is a slave only device and uses the SMBus/SPI INTERRUPT to signal the host device that it wants to talk. The SMBus/SPI INTERRUPT on the ADT7316/17/18 is used as an over/under limit indicator.
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PRELIMINARY TECHNICAL DATA ADT7316/7317/7318
Outline Dimensions (Dimensions shown in inches and mm ) 16-Lead QSOP Package ( RQ-16 )
0.19 7 (5.00) 0.18 9 (4.80)
16
9
0.157 (3.99) 0.150 (3.81)
1 8
0.24 4 (6.20) 0.22 8 (5.79)
P IN 1 0 .059 (1.50 ) MAX 0.069 (1.75) 0.053 (1.35)
0.010 (0.25) 0.004 (0.10)
0.025 (0.64) BSC
0 .012 (0.30 ) 0 .008 (0.20 )
SEATING PLANE
0.010 (0.20) 0.007 (0.18)
8o 0o
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